Familiarize with 8051 Architecture

Program Counter and Data Pointer

The 8051 contains two 16-bit registers-the program counter(PC) and data pointer(DPTR). Each is used to hold the address of a byte in memory. Program instruction bytes are fetched from locations in memory that are addressed by PC. Program ROM may be on the chip at address 000h to 0FFFh, external to the chip for addresses from 0000h to FFFFh. The PC is automatically incremented after every instruction bytes is fetched and may also be altered by certain instructions. The PC is the only register that does not have an external address.

The DPTR register is made up of two 8-bit registers named DPH and DPL which are used to furnish memory address for internal and external code access. The DPTR is under control of program instructions and can be specified by its 16-bit name DPTRor by each individual byte name, DPH and DPL. DPTR does not have a single internal address: DPL and DPH are each assigned an address.

A and B CPU registers

The 8051 contains 34 general-purpose, or working registers. Two of these registers A and B hold result of many instructions, particularly math and logical operations, of the 8051 CPU. Other registers are arranged as part of internal RAM in four banks, B0-B3, of eight registers and comprise the mathematical operator. The accumulator is most versatile of the two CPU registers and is used for many operations including addition, subtraction, multiplication, and division, and boolean manipulations. The A register is also used for all data transfers between the 8051 and any external memory. The B register is used with the A register for multiplication and division operations and has no other function than as location where data may be stored.

Flags and Program Status Word

Flags are 1-bit registers provided to store results of certain program instructions. Other instructions can test the condition of the flags and make decisions based on flags states. In order that the flag may be conveniently addressed, they are grouped inside the Program Status Word(PSW) and Power Control registers(PCON) registers.

•The 8051 has 4 math flags that respond automatically to outcomes of math operations and three general purpose user flags that can set to 1 or cleared to 0 by the programmer as desired. The math flags include carry(Cs), Auxillary carry(AC), Overflow(OV) and Parity(P).
User defined flags are;
•F0
•GF0 and
•GF1
These are general purpose flags that may be used by programmer to record some events in the program. All of the flags can be set and cleared by the programmer at will. The math flags however affected by math operators.

The program status word shown in figure contains math flags, user program flag F0 and register select bits that identify which of the four general purpose register banks is currently in use by the program. The remaining two user flags are stored in PCON register. The following figure shows Program Status Word of 8051.

CY	AC	F0	RS1	RS0	OV	-	P

The table below shows the functions of PSW bits.

Bit	Symbol	Function
7	CY	Carry flag used for arithmetic, jump, rotate and boolean instructions
6	AC	Auxillary carry flag; used for BCD arithmetic
5	F0	User flag 0
4	RS1	Register bank select bit 1
3	RS0	Register bank select bit 0
2	OV	Overflow flag used with arithmetic instruction
1	-	Reserved for future use
0	P	Parity flag: Shows Parity of Accumulator;1=odd parity

As we all know there is 4 register banks for 8051 which can be selected by setting and clearing RS0 and RS1 as shown below:

RS1	RS0	Function
0	0	Select register bank 0
0	1	Select register bank 1
1	0	Select register bank 2
1	1	Select register bank 3

 The 8051 has 128 byte of RAM. We can see internal RAM organization i next figure, and it is organized into 3 different areas.

1.32-bytes from 00H to 1FHthat make up 32 working registers organized as four banks of  eight registers each.

The 4 register banks are numbered 0 to 3 and are made up of 8 registers named R0 to R7. Each register can be addressed by name (when it's bank is selected) or by its RAM address. Thus R0 of bank 3 is R0(if bank 3 is currently selected) or address 18H(whether bank 3 is selected or not). Bit RS0 and RS1 in PSW determine which bank of registers is currently in use at any time when the program is running. Register banks not selected can be used as general purpose RAM.

Bank 0 is selected on power on reset.

2. A bit addressable area of 16-bytes occupies RAM byte addresses 20H to 2FH, forming a total of 128 addressable bits. An addressable bit may be specified by its its bit address of 00H to 7FH, or 8-bits may from any byte address from 20H to 2FH.

Thus, for example, bit address 4FH is also bit 7 of byte 29H. Addressable bits are useful when the program need only remember a binary event(switch on, light off). Internal RAM is a short supply as it is, so why use a byte when a bit will do the work?

3. A general purpose RAM area above the bit-area, area from 30H to 7FH, adressable as bytes. This area is normally known as scratch pad area.
If you don't get the idea see the picture below;

Stack and Stack Pointer

The stack refers to an area of internal RAM that is used in conjunction with certain opcodes to store and retrieve data quickly. The 8-bit stack pointer(SP) register is used by the 8051 to hold an internal RAM address that is called the top of stack. The address held in stack pointer register is the location in internal RAM where the last byte of  data was stored by a stack operation. When data is to be placed on the stack, the SP increments before storing data on the stack so that the stack grows ipad data stored. As data retrieved from stack, the bytes read from the stack, and then the SP decrements to point to the next available byte of stored data.

Operation of the stack and the SP is shown in next figure. The SP is set to 07H when the 8051 is reset and can be changed to any internal RAM address by the programmer, using data move command.

The stack is limited in height to the size of the internal RAM. The stack has the potential(if the programmer is not careful to limits its growth) to overwrite valuable data in the register banks, bit-addressable RAM, and scratch pad RAM areas. The programmer is responsible for making sure the stack does not grow beyond predefined bounds.

The stack is normally placed in high internal RAM, by an appropriate choice of the number placed in the SP register, to avoid conflict with the register, bit, and scratch pad internal RAM areas.