electronics4u

Derivation of Frequency of Oscillation We have to find out the transfer function of RC feedback network. Feedback Circuit of RC Phase Shift Oscillator Applying KVL to various loops on the figure, we get, $$I_1 \left(R+\frac{1}{j \omega C }\right) -I_2R=V_i \text{ ....(1)}$$ $$-I_1R+I_2\left (2R+\frac {1}{j\omega C}\right)-I_3R=0\text{ ... (2)}$$ $$0-I_2R+I_3\left(2R+ \frac{1}{j\omega C}\right)=0\text{ ...(3)}$$ Replacing \(j\omega\) with \(s\) and writing equations in the matrix form, $$\begin{bmatrix}R+\frac{1}{sC} & -R & 0 \\-R & 2R+\frac{1}{sC} & -R \\0 & -R & 2R+\frac{1}{2sC} \end{bmatrix}\begin{bmatrix}I_1\\I_2\\I_3\end{bmatrix}=\begin{bmatrix}V_i\\0\\0\end{bmatrix}$$ Using Cramer's rule to find out \(I_3\), $$\text{Let, }D=\begin{bmatrix}R+\frac{1}{sC} & -R & 0 \\-R & 2R+\frac{1}{sC} & -R \\0 & -R & 2R+\frac{1}{2sC} \end{bmatrix}$$ \(|D|=\begin{vmatrix}R+\frac{1}{sC} & -R & 0 \\-R & 2R+\frac{1}{

Hai friends, today we will discuss more about LaTeX commands. I am not going to exaggerate things. I will show you the facts straight forward. Fonts Use \mathbb or \Bbb for "black board bold" font. \(\mathbb{ A B C D E F G H I J K L M N O}\) Use \mathbf for "bold face" font. \(\mathbf{ A B C D E F G H I J K L M N O}\) Use \mathtt for "typewriter" font. \(\mathtt{ A B C D E F G H I J K L M N O}\) Use \mathrm for "roman" font. \(\mathrm{ A B C D E F G H I J K L M N O}\) Use \mathsf for "sans-serif" font. \(\mathsf{ A B C D E F G H I J K L M N O}\) Use \mathcal for "calligraphic" script. \(\mathcal{ A B C D E F G H I J K L M N O}\) Use \mathfrak for "Fraktur"(old German style letters). \(\mathfrak{ A B C D E F G H I J K L M N O}\) \(\mathbb{ A B C D E F G H I J K L M N O}\) \(\mathbf{ A B C D E F G H I J K L M N O}\) \(\mathtt{ A B C D E F G H I J K L M N O}\) \(\mathrm{ A B C D E F G H I J K L M

AND Gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and_gate is port(   a,b : in std_logic;   s : out std_logic ); end and_gate; architecture Behavioral of and_gate is begin s<=a and b; end Behavioral; OR Gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity or_gate is port(   a,b : in std_logic;   s : out std_logic ); end or_gate; architecture Behavioral of or_gate is begin s<=a or b; end Behavioral; NOT Gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity not_gate is port(   a : in std_logic;   s : out std_logic ); end not_gate; architecture Behavioral of not_gate is begin s<=not(a); end Behavioral; NAND Gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity nand_gate is port(   a,b : in std_logic;   s : out std_logic ); end nand_gate; architecture Behavioral of nand_gate is begin s<=a nand b; end Behavioral; NOR Gate library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity nor_gate is port(   a,b : in std_logic;   s : out std_logic )

What is Mathjax? MathJax allows you to include mathematics in your web pages, either using LaTeX, MathML, or AsciiMath notation, and the mathematics will be processed using JavaScript to produce HTML, SVG or MathML equations for viewing in any modern browser. Installing MathJax on Your Website The easiest way to install MathJax on your website is adding link of CDN(Content Distribution/Delivery Network) inside the head section of your website. You copy and paste following code just above closing head tag. You can place following code on body part of your website too. If you are using Blogger as your blogging platform you can add this code on your HTML post editor. It is not necessary to add this code for each post. You can add this code by adding HTML/JavaScript gadget for this script stored on CDN.  I added this code along with the codes of contact button. Let us Start MathJax The support for  TeX  and  LaTeX  in MathJax consists of two parts: the tex2jax preprocesso

Requirements Voltage Gain: 50 Required output voltage swing: 10V Selection of Transistor Select transistor BC107 since minimum guaranteed \(h_{FE}\)(=100) is more than the required gain(=50) of the amplifier. Quick Reference Through BC107 Type: NPN Silicon Application: In audio frequency Maximum Ratings: \(V_{CB}=50V, V_{CE}=45V,\\ V_{EB}=6V, I_C=100mA\) Nominal Ratings: \(V_{CE}=5V,  I_c=2mA, h_{FE}=100 \text{ to } 500\) CE amplifier circuit diagram DC Biasing Conditions \(V_{CC}\) is taken as \(20\%\) more than required output voltage swing. Hence \(V_{CC}=12V\). \(I_c=2mA\), because \(h_{FE}\) is guaranteed 100 at that current as per data sheet. In order to make the operating point at the middle of the load line, assume the DC conditions as follows: \(V_{RC}=40\% \text{ of } V_{CC}=4.8V\) \(V_{RE}=10\% \text{ of } V_{CC}=1.2V\) \(V_{CE}=50\% \text{ of } V_{CC}=6V\) Design of \(R_C\) \(V_{RC}=I_C×R_C=4.8V\). From this we get \(R_C=2.4K\Omega.\text{ Us

The 8086 microprocessor uses a 20-bit address to access memory. With 20-bit address the processor can generate 2 20 = 1 Mega address. The basic memory word size of the memories used in the 8086 system is 8-bit or 1-byte (i.e., in one memory location an 8-bit binary information can be stored). Hence, the physical memory space of the 8086 is 1Mb (1 Mega-byte). For the programmer, the 8086 memory address space is a sequence of one mega-byte in which one location stores an 8-bit binary code/data and two consecutive locations store 16-bit binary code/data. But physically (i.e., in the hardware), the 1Mb memory space is divided into two banks of 512kb (512kb + 512kb = 1Mb). The two memory banks are called Even (or Lower) bank and Odd (or Upper) bank. The organization of even and odd memory banks in the 8086-based system is shown in Figure. The 8086-based system will have two sets of memory IC's. One set for even bank and another set for odd bank. The data lines D 0 -D 7 are conne

Maximum mode signals The maximum mode signals of 8086 are listed in table below. The 8086 can made to work in maximum mode by grounding MN/ MX . In maximum mode, the pin 24 to pin 31 are defined as follows. Name Description/Function Type RQ / GT 1 , RQ / GT 0 Request/Grant bus access control Bidirectional LOCK Bus priority block control Output, Tristate S 2 , S 1 , S 0 Bus cycle status Output, Tristate QS 1 , QS 0 Instruction queue status Output S 0 , S 1 , S 2 : These are status signals and they used by the 8288 bus controller to generate the bus timing and control signals. The status signals are decoded as shown in table: Status Signal Machine Cycle S 2 S 1 S 0 0 0 0 Interrupt acknowlegement 0 0 1 Read IO port 0 1 0 Write IO port 0 1 1 Halt 1 0 0 Code access 1 0 1 Read memory 1 1 0 Write memory 1 1 1 Passive/Inactive RQ / GT 0 , RQ / GT 1 (Bus Request/Bus Grant): These reques

Minimum Mode Signals The minimum mode signals of an 8086 are listed in table below. For minimum mode of operation the MN/ MX pin is tied to V cc (logic high). In minimum mode, the 8086 itself generates all bus control signals. The minimum mode signals are explained below: Name Description/Function Type HOLD Hold request Input HLDA Hold acknowledgement Output WR Write control Output, Tristate M/ IO Memory/IO control Output, Tristate DT/ R Data transmit/Recieve Output, Tristate DEN Data enable Output, Tristate ALE Address latch enable Output INTA Interrupt acknowledge Output DT/ R (Data Transmit/Receive): It is an output signal from the processor to control the direction of data flow through the data transceivers. DEN (Data Enable) : It is an output signal from the processor used as output enable for the data transceivers. ALE(Address Latch Enable): It is used to demultiplex the address and data lines using external lat

8086 Pin Out Diagram 8086 Pin Out Diagram The signals of 8086 microprocessor is classified into three. They are common mode signals, minimum mode signals, and maximum mode signals. Common mode signals The lower sixteen lines of the address are multiplexed with data and the upper four lines of the address are multiplexed with status signals. During the first clock period of a bus cycle the entire 20-bit address is available on these lines. During all other clock periods of a bus cycle, the data and status signals will be available on these lines. Name Description/Function Type AD 15 -AD 0 Address/Data Bidirectional, Tristate A 19 /S 6 -A 16 /S 3 Address/Status Output/Tristate BHE /S 7 Bus High Enable/Status Output/Tristate MN/ MX Minimum/Maximum mode control Input RD Read Control Output, Tristate TEST Wait on test control Input READY Wait state control Input RESET System reset Input NMI Non-maskable interrupt request Inpu

Memory Segmentation Two type of memory organisations are commonly used. These are linear addressing  and segmented addressing . In linear addressing the entire memory space is available to the processor in one linear array. In the segmented addressing, on the other hand, the available memory space is divided into " chunks " called segments. Such a memory is known as segmented memory. In 8086 system the available memory space is 1Mbytes . This memory is divided into number of logical segments. Each segment is 64 K bytes in size and addressed by one of the segment registers. The 16-bit contents of the segment register give starting/base address of a particular segment, as shown in Figure. To address a specific memory location within a segment we need an offset address. The offset address is also 16-bit wide and it is provided by one of the associated pointer or index register. Memory Segmentation Rules of memory Segmentation  The four can overlap for small pro