ADC Rd, Rr
;Add with Carry two Registers
0≤d≤31, 0≤r≤31;Rd← Rd + Rr+C
Type: Arithmetic instruction Adds two registers and the contents of the C flag and places the result in the diestination register Rd. Flags: H, S, V, N, Z, C Cycles: 1 Example: ;Add R1:RO to R3:R2 add r2,r0 ;Add low byte adc r3,r1 ;Add with carry high byte
ADD Rd, Rr
;Add two Registers
0≤d≤31, 0≤r≤31;Rd← Rd + Rr
Type: Arithmetic instruction Adds two registers without the C flag and places the result in the destination register Rd. Flags: H, S, V, N, Z, C Cycles:1 Example: add r1, r2 ;Add r2 to r1 (r1=r1+r2) add r28,r28 ;Add r28 to itself (r28=r28+r28)
ADIW Rdl,K
;Add Immediate to Word
d∊{24, 26, 28, 30}, 0≤K≤63;Rdh:Rdl← Rdh:Rdl + K
Type: Arithmetic instruction Adds an immediate value (0-63) to a register pair and places the result in the register pair. This instruction operates on the upper four register pairs, and is well suited for operations on the pointer registers. Flags: S, V, N, Z,C Cycles:2 Example: adiw r25:24,1 ;Add 1 to r25:24 adiw ZH:ZL, 63 ;Add 63 to the Z-pointer (r31:r30)
AND Rd, Rr
;Logical AND Registers
0≤d≤31, 0≤r≤31;Rd← Rd * Rr
Type: Logical Instruction Performs the logical AND between the contents of register Rd and register Rr and places the result in the destination register Rd. Flags: S, V← 0. N, Z Cycles: 1 Example: and r2,r3 ;Bitwise and r2 and r3,result in r2 ldi r16,1 ;Set bitmask 0000 0001 in r16 and r2,r16 ;Isolate bit 0 in r2
ANDI Rd, K
;Logical AND Register and Constant
16≤d≤31, 0≤K≤255; Rd← Rd * K
Type: Logical Instruction Performs the logical AND between the contents of register Rd and a constant and places the result in the destination register Rd. Flags: S, V←O, N, Z Cycles: 1 Example: andi r17 ,$0f ;clear upper nibble of r17 andi r18, $10 ;isolate bit 4 in r18
ASR Rd
;Arithmetic Shift Right
0≤d≤31
;Rd(n) ← Rd(n+1), n=0 to 6
Type: Bitwise Operation
Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C flag of the SREG. This operation effectively divides a signed value by two without changing its sign. The Carry flag can be used to round the result.Flags: S, V, N, Z, C Cycles: 1
Example:
ld1 r16,$lO ;Load decimal 16 into r16
asr r16 ;rl6=r16 / 2
ldl r17,$FC ;Load -4 in r17
asr r17 ;r17=r17/2
BCLR s
;Flag Clear
0≤s≤7
;SREG(s) ← 0
Type: Bitwise Operation
Clears a single flag in SREG (Status Register).
Flags: I, T, H, S, V, N, Z, C Cycles: 1
Example:
bclr 0 ;Clear Carry flag
bclr 7 ;Disable interrupts
BLD Rd, b
;Bit load from T to Register
0≤d≤31, 0≤b≤7
;Rd(b) ← T
Type: Bitwise Operation
Copies the T flag in the SREG (Status Register) to bit b in register Rd.
Flags: None Cycles: 1
Example:
bst r1,2 ;Store bit 2 of r1 in T flag
bld r0,4 ;Load T flag into bit 4 of r0
BRBC s, K
;Branch if Status Flag Cleared
0≤s≤7, -64≤K≤+63
;if (SREG(s) = 0) then PC←PC+K + 1
Type: Branch instruction
Conditional relative branch. Tests a single bit in SREG (Status Register) and branches relatively to PC if the bit is set.
Flags: None Cycles: lor2
Example:
cpi r20,5 ;compare r20 to the value 5
brbc 1,noteq ;Branch if Zero flag cleared
...........
noteq:nop ;Branch destination (do nothing)
BRBS s, K
;Branch if Status Flag Set
0≤s≤7, -64≤K≤+63
;if (SREG(s) = 1) then PC←PC+K + 1
Type: Branch instruction
Conditional relative branch. Tests a single bit in SREG (Status Register) and branches relatively to PC if the bit is set.
Flags: Cycles: 1 or 2
Example:
bst r0,3 ;Load T bit with bit 3 of r0
brbs 6,bitset ;Branch T bit was set
........
bitset: nop ;Branch destination (do nothing)
BRCC K
;Branch if Carry Cleared
-64≤K≤+63
;if (C = 0) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is cleared.
Flags: None Cycles: 1 or2
Example:
add r22,r23 ;Add r23 to r22
brcc nocarry ;Branch if carry flag cleared
...........
nocarry: nop ;Branch destination (do nothing)
BRCS K
;Branch if Carry Set
-64≤K≤+63
; if (C = 1) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is set.
Flags: None Cycles: 1 or 2
Example:
cpi r26,$56 ;Compare r26 with $56
brcs carry ;Branch if carry set
carry: nop ;Branch destination (do nothing)
BREAK
Type: MCU Control Instruction
The BREAK instruction is used by the on-chip debug system and is normally not used in the application software. When the BREAK instruction is executed, the AVR CPU is set in the stopped mode. This gives the on-chip debugger access to intemal resources.
Flags: None Cycles: 1 or N/A
BREQ K
;Branch if Equal
-64≤K≤+63
;if (Z = 1) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Zero flag (Z) and branches relatively to PC if Z is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur if and only if the unsigned or signed binary number represented in Rd was equal to the unsigned or signed binary number represented in Rr.
Flags: None Cycles: 1 or 2
Example:
ccp r1,r0 ;Compare registers r1 and r0
breq equal ;Branch if registers equal
equal: nop ;Branch destination (do nothing)
BRGE K
; Branch if Greater or Equal (Signed)
-64≤K≤+63
;if (N ⊕ V= 0) then PC ← PC + K+ 1
Type: Branch instruction
Conditional relative branch. Tests the Signed flag (S) and branches relatively to PC if S is cleared. If the instruction is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur if and only if the signed binary number represented in Rd was greater than or equal to the signed binary number represented in Rr.
Flags: None Cycles: 1 or 2 Example:
cp r11,r12 ;Compare reglsters r11 and r12
brge greateq ;Branch if r11 ≥ r12 (Signed)
.............
greateq: nop ;Branch destination (do nothing)
BRHC K
;Branch if Half Carry Flag Cleared
-64≤K≤+63
;if (H = 0) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Half Carry flag (H) and branches relatively to PC if H is cleared.
Flags: None Cycles: 1 or2
Example:
brhc hcleaz ;Branch if Half Carry flag cleared
...............
hclear:nop ;Branch destination (do nothing)
BRHS K
;Branch if Half Carry Flag Set
-64≤K≤+63
;if (H = 1) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Half Carry flag (H) and branches relatively to PC if H is set.
Flags: None Cycles: 1 or 2
Example:
brhs hset ;Branch if Half Carry flag set
..........
hset:nop ;Branch destinatzon (do nothing)
BRID K
; Branch if Interrupt Disabled
-64≤K≤+63
;if ( I = 0) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Global Interrupt flag (I) and branches relatively to PC if I is cleared.
Flags: None Cycles: 1or 2
Example:
brid intdis ;Branch if interrupt disabled
...............
intdis:nop ;Branch destination (do nothing)
BRIE K
;Branch if Interrupt Enabled
-64≤K≤+63
;if ( I = 1) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Global Interrupt flag (I) and branches relatively to PC if I is set.
Flags: None Cycles: 1 or 2
Example:
brie inten ;Branch if interrupt enabled
..............
inten: nop ;Branch destination (do nothing)
BRLO K
; Branch if Lower(Unsigned)
-64≤K≤+63
;if (C = 1) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB, or SUBI, the branch will occur if and only if the unsigned binary number represented in Rd was smaller than the unsigned binary number represented in Rr.
Flags: None Cycles: 1or 2
Example:
eor r19,rl9 ;Clear :19
loop: inc r19 ;Increment r19
................
cpi r19,$10 ;Compare r19 with $10
brlo loop ;Branch if r19 < $10 (unsigned)
nop ;Exit from loop (do nothing)
BRLT K
; Branch if Less Than Zero, Signed
-64≤K≤+63
;if (N ⊕ V= 1) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Signed flag (S) and branches relatively to PC if S is set. If the instruction is executed immediately after any of the instructions CP. CPI, SUB, or SUBI, the branch will occur if and only if the signed binary number represented in Rd was less than the signed binary number represented in Rr.
Flags: None. Cycles: 1 or 2
Example:
bcp r16,r1 ;Conpare r16 to r1
brlt less ;Bzanch if r16 < r1 (Signed)
.................
less: nop ;Branch destination (do nothing)
BRMI K
; Branch if Minus
-64≤K≤+63
; if (N = 1) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Negative flag (N) and branches relatively to PC if N is set.
Flags: None Cycles: 1 or 2
Example:
subi r18,4 ;Subtract 4 from r18
brmi negative ;Branch if result negative
negative: nop ;Branch destinatton (do nothtng)
BRNE K
; Branch if Not Equal
-64≤K≤+63
;if (Z = 1) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Zero flag (Z) and branches relatively to PC if Z is cleared. If the instruction is executed immediately after any of the instructions CP, C Pl. SUB. or SUBl. the branch will occur if and only if the unsigned or signed binary number represented in Rd was not equal to the unsigned or signed binary number represented in Rr.
Flags: None Cycles: 1 or 2
Example:
eor r27,r27 ;Clear r27
loop: inc r27 ;Increment r27
...............
cpi r27,5 ;Compare r27 to 5
brne loop ;Branch if r27 not equal 5
nop ;Loop exit (do nothing)
BRPL K
; Branch if Plus
-64≤K≤+63
;if (N = 0) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Negative flag (N) and branches relatively to PC if N is cleared.
Flags: None Cycles: 1 or 2
Example:
subi r26,$50 ;Subtract $50 from r26
brpl positive ;Branch if r26 positive
...............
positive: nop ;Branch destination (do nothing)
BRSH K
; Branch if Same or Higher
-64≤K≤+63
;if (C = 0) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is cleared. If the instruction is executed immediately after execution of any of the instructions CP, CPl, SUB, or SUBI, the branch will occur if and only if the unsigned bina
ry number represented in Rd was greater than or equal to the unsigned binary number represented in Rr.
Flags: None Cycles: 1 or 2
Example:
subi r19,4 ;Subtract 4 from r19
brsh highsm ;Branch if r19 >4 (unsigned)
................
highsm: nop ;Branch destination (do nothing)
BRTC K
;Branch if T Flag Cleared
-64≤K≤+63
;if (T = 0) then PC ← PC + K + 1
Type: Branch instruction
Conditional relative branch. Tests the T flag and branches relatively to PC if T is cleared.
Flags: None Cycles: 1 or 2
Example:
bst r3,5 ;Store bit 5 of r3 in T flag
brtc tclear ;Branch it this bit was cleared
...............
tclear: nop ;Branch destination (do nothing)
BRTS K
; Branch if T Flag Set
-64≤K≤+63
;if (T = 1) then PC ← PC + k + 1
Type: Branch instruction
Conditional relative branch. Tests the T flag and branches relatively to PC if T is set.
Flags: None Cycles: 1 or 2
Example:
bst r3,5 ;Store bit 5 of r3 in T flag
brts tset ;Branch if this bit was set
..........
tset: nop ;Branch destination (do nothing)
BRVC K
; Branch if Overflow Flag is Cleared
-64≤K≤+63
;if (V = 0) then PC ← PC + k + 1
Type: Branch instruction
Conditional relative branch. Tests the Overflow flag (V) and branches relatively to PC if V is cleared.
Flags: None Cycles: 1 or 2
Example:
add r3,r4 ;Add r4 to r3
brvc noover ;Branch if no overflow
..............
noover: nop ;Branch destination (do nothing)
BRVS K
;Branch if Overflow Flag is Set
-64≤K≤+63
;if (V = 1) then PC ← PC + k + 1
Type: Branch instruction
Conditional relative branch. Tests the Overflow flag (V) and branches relatively to PC if V is set.
Flags: None Cycles: 1 or 2
Example:
add r3,r4 ;Add r4 to r3
brvs overfl ;Branch if overflow
..........
overfl: nop ;Branch destination (do nothing)
BSET s
;Bit set in SREG
0≤s≤7
;SREG(s) ← 1
Type: Bit and bit test instruction
Sets a single flag or hit in SREG (Status Register).
Flags: Any of the flags of Status register Cycles: 1
Example:
bset 6 ;Set T flag
bset 7 ;Enable interrupt
BST Rr, b
;Bit Store from Register to T
0≤r≤31, 0≤b≤7
;T ← Rr(b)
Type: Bit and bit test instruction
Stores bit b from Rd to the T flag in SREG (Status Register).
Flags: T Cycles: 1
Example: ;Copy bit
bst r1,2 ;Store bit 2 of r1 in T flag
bld r0,4 ;Load T into bit 4 of t
CALL K
; Long Call to a Subroutine
0≤K<64K(Devices with 16-bit PC) or 0≤K<4M(Devices with 22-bit PC)
Type: Branch instruction
Calls to a subroutine within the entire program memory. The return address (to the instruction after the CALL) will be stored onto the stack. (See also RCALL). The stack pointer uses a post-decrement scheme during CALL.
Flags: None Cycles: 4
Example:
mov r16,r0 ;copy r0 to r16
call check ;Call subroutine
nop ;Continue (do nothing)
............
check:cpi r16,$42 ;Check if r16 has a special value
breq error ;Branch if equal
ret ;Return from subroutine
..............
error : rjmp error ;Infinite loop
CBI P,b
;Clear Bit in I/O Register
0≤P≤31, 0≤b≤7
;I/O(P,b) ← 0
Type: Bit and bit test instruction Clears a specified bit in an I/O Register. This instruction operates on the lower 32 I/O registers (addresses 0-31).
Flags: None Cycles:2
Example:
cbi $12,7 ;Clear bit 7 in Port D
CBR Rd,K
;Clear Bit(s) in Register
16≤d≤31, 0≤K≤255
;Rd ← Rd * ($FF - K)
Type: Bit and bit test instruction Clears the specified bits in register Rd. Performs the logical AND between the contents of register Rd and the complement of the constant mask K.
Flags: S, N, V ←0, Z Cycles: 1
Example:
cbr r16,$F0 ;Clear upper nibble of r16
cbr r18,1 ;Clear bit 0 in r18
CLC
;Clear Carry
;C ← 0
Type: Bit and bit test instruction Clears the Carry flag (C) in SREG (Status Register).
Flags: C ← 0 Cycles: 1
Example:
add r0,r0 ;Add r0 to itself
clc ;Clear Carry flag
CLH
;Clear Half Carry Flag in SREG
;H ← 0
Type: Bit and bit test instruction Clears the Half Carry flag (H) in SREG (Status Register).
Flags: H ← 0. Cycles: 1
Example:
clh ;clear the Half Carry flag
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