Architecture of Intel 8086

8086 Block Diagram

Figure shows internal architecture of 8086. It is internally decided into two functional units:

• Bus Interface Unit(BIU)
• Execution Unit

These functional units can work simultaneously to increase the system speed and hence the throughput. Throughput is the measure of instruction executed per unit time.

8086 Internal Architecture Block Diagram

1. Bus Interface Unit(BIU)

The bus interface unit is the 8086's interface to the outside world. It provides a full 16-bit bi-directional data bus and 20-bit address bus. The BIU is responsible for performing all external bus operations, as listed below.

Functions of Bus Interface Unit

1. t sends address of memory or I/O
2. It fetches instruction from memory.
3. It reads data from port/memory.
4. It writes data into port/memory.
5. It supports instruction queueing.
6. It provides the address relocation facility.

To implement these functions the BIU contains, the instruction queue, segment registers instruction pointer. address summer and bus control logic.

1.1 Instruction Queue

To speed up program execution, the BIU fetches six instruction bytes ahead of time from the memory. These prefetched instruction bytes are held for the execution unit in a group of registers called Queue. With the help of queue it is possible to fetch next instruction when current instruction is in execution. For example, current instruction in execution is a multiplication instruction. In 8086, operands for multiplication operations are within registers. Still it requires 100 clock cycles to execute multiply instruction. Like multiplication there are number of other instructions in 8086 which need quite a large number of clock cycles for execution. During this execution time the BIU fetches the next instruction or instructions from memory into the instruction queue instead of remaining idle. The BIU continues this process as long as the queue is not full. Due to this, execution unit Sets the ready instruction in the queue and instruction fetch time is eliminated. This is illustrated in figure below.

Pipelining

The queue operates on the principle first in first out (FIFO). So that the execution unit gets the instructions for execution In the order they are fetched. In case of JUMP and CALL instructions, instruction already fetched in queue are of no use. Hence, in these cases queue is dumped and newly formed by Ioading instructions from new address specified by JUMP or CALL instruction. Feature of fetching the next instruction while the current instruction is executing is called pipelining.

The length of the queue should be such that EU should get the next instruction from the queue of the BIU immediately after the execution of the current instruction. To satisfy this, number of pre-fetched instruction in the queue and hence the queue length depends on the fetching speed and the execution speed. Sometime queue length may be restricted due to the space available on the CPU chip.

2. Execution Unit

The execution unit of 8086 tells the BIU from where to fetch instructions or data, decodes instructions and executes instructions. It contains:

• Control Circuitry
• Instruction Decoder
• Arithmetic Logic Unit (ALU)
• Register Organization
• Flag Register
• General Purpose Registers
• Pointers and Index Registers

Control circuitry, Instruction decoder, ALU

The control circuitry in the EU directs the internal operations. A decoder in the EU translates the instructions fetched from memory into a series of actions which the EU performs. ALU is 16-bit It can add. subtract, AND, OR, XOR, increment, decrement, complement and shift binary numbers.

2.1 Register Organisation

The 8086 has a powerful set of registers. It includes general purpose registers, segment registers, pointers and index registers, and flag register. The figure shows the register organisation of 8086. It is also known as programmer's model of 8086. Tne registers shown in programmer's model are accessible lo programmer. As shown in the Figure all the registers of 8086 are 16-bit registers.

Register Organisation in 8086

2.2 General Purpose Registers

The 8086 has four 16-bit general purpose registers labeled AX, BX, CX and DX. Each 16-bit general purpose register can be split into two 8-bit registers. The letters L and H specify the lower and higher bytes of a particular register. For example, BH means the higher order byte (8-bits) of the BX register and BL means the lower byte(8-bits) of the BX register. The letter X is used to specify the complete 16-bit register.

The general purpose registers are either used for holding data, variables and intermediate results temporarily. They can also be used as a counters or used for storing offset address for some particular addressing modes. the register AX is used as 16-bit accumulator whereas register AL (lower byte of AX) is used as 8-bit accumulator. The register BX is also used as offset storage for generating physical addresses in case of certain addressing modes. On the other hand, the register CX is also used as a default counter in case of string and loop instructions.

2.3 Segment Registers

The physical address of the 8086 is 20-bits wide to access 1 Mb memory locations. However, its registers and memory locations which contain logical addresses are just 16-bits wide. Hence 8086 uses memory segmentation. It treats the 1 Mb of memory as divided into segments. with a maximum size of a segment as 64 Kb. Thus any location within the segment can be accessed using 16 bits. The 8086 allows only four active segments at a time as shown in figure. For the selection of the four active segments the 16-bit registers are provided by the BIU of 8086. These four registers are:

Memory Segmentation and Segment Registers

Code segment (CS) register, the data segment (DS) register, the stack segment (SS) register, and the extra segment (ES) register. These are used to hold the upper 16-bits of the starting addresses of the four memory segments, on which 8086 works at a particular time. For example, the value in CS identifies the starting address of 64 Kb segment known as code segment. By "starting address", we mean the lowest addressed byte in the active code segment. The starting address is also known as base address or 'segment base'.

The BIU always inserts zeros for the lower 4 bits (nibble) in the contents of segment register to generate 20-bit base address. For example, if the code segment register contains 488AH, then code segment will start at address 488A0H.

Functions of Segment Registers

• The CS register holds the upper l6-bits of the starting address of the segment from which the BIU is currently fetching the instruction code byte.
• The SS register is used for the upper 16-bits of the starting address for the   program stack (all stack related instructions will operate on stack).
• ES register and DS are used to hold the upper 16-bits of the starting address of two memory segments which are used for data.

2.4 Pointers and Index Registers

All segment registers are 16-bit wide. But it is necessary to generate 20-bit address (physical address) on the address bus. To get 20-bit physical address one or more pointer or index registers are associated with each segment register. The pointer registers IP, BP and SP are associated with code, data and stack segments, respectively. They hold the offset within Ihe code, data and stack segments, respectively. The index registers DI and SI are used as a general purpose registers as well as for offset storage in case oI indexed, based indexed and relative based indexed addressing modes.

2.5 Flag Registers

A flag is a flip-flop which indicates some condition produced by the execution of an Instruction or contain certain operations of the EU. The flag register contains 9 active flags as shown in figure. Six of them are used to indicates some conditions produced by instruction.

X	X	X	X	OF	DF	IF	TF	SF	ZF	X	AF	X	PF	X	CF
								8085 compatible flags

1. Carry Flag (CF) : In case of addition this flag is set if there is a carry out of the MSB. The carry flag also serves as a borrow flag for subtraction. In case of subtraction it is set when borrow is needed.
2. Parity Flag(PF): It is set to 1 if result of byte operation or lower byte of the word operation contain an even number of ones; otherwise it is zero.
3. AuxIliary Carry Flag (AF): This flag is set if there is an overflow out of bit 3  i.e., carry from lower nibble to higher nibble (D3 bit to D0 bit). This flag is used for BCD operations and it is not available for the programmer.
4. Zero Flag (ZF): The zero flag; sets if the result of operation in  ALU  is zero and flag resets if the result is nonzero. The zero flag is also set if a certain register content becomes zero following an increment or decrement operation of that register.
5. Sign Flag(SF): After the execution of arithmetic or logical operations. If the MSB of the result is 1, the sign bit is set. Sign bit 1 indicates the result is negative; otherwise it is positive.
6. Overflow Flag (OF): This flag is set if result is out of range. For addition this flag is set when there is a carry into the MSB and no carry out of the MSB or vice-versa. For subtraction, it is set when the MSB needs a borrow and there is no borrow from the MSB, or vice-versa.

The three remaining flags are used to control certain operations of the processor.


7. Trap Flag (TF):  One way to debug a program is to run the program one instruction at a time and see the contents of used registers and memory variables after execution of every instruction. This process is called "single stepping" through a program. Trap flag is used for single stepping through a program. If set, a trap is executed after execution of each instruction, i.e., interrupt service routine is executed which displays various registers and memory variable contents on  the display after execution of each instruction. Thus programmer can easily trace and correct errors in the program.
8. Interrupt Flag (IF): It is used to allow/prohibit the interruption of a program. If set, a certain type of interrupt (a maskable interrupt) can be recognized by the 8086; otherwise, these interrupts are ignored.
9. Directlon Flag (DF): It is used with string instructions. If DF= O, the string is processed from its beginning with the first element having the lowest address. Otherwise, the string is processed from the high address towards the low address.