8086 Common Mode Signals

8086 Pin Out Diagram

The signals of 8086 microprocessor is classified into three. They are common mode signals, minimum mode signals, and maximum mode signals.

Common mode signals

The lower sixteen lines of the address are multiplexed with data and the upper four lines of the address are multiplexed with status signals. During the first clock period of a bus cycle the entire 20-bit address is available on these lines. During all other clock periods of a bus cycle, the data and status signals will be available on these lines.

Name	Description/Function	Type
AD₁₅-AD₀	Address/Data	Bidirectional, Tristate
A₁₉/S₆-A₁₆/S₃	Address/Status	Output/Tristate
BHE /S₇	Bus High Enable/Status	Output/Tristate
MN/MX	Minimum/Maximum mode control	Input
RD	Read Control	Output, Tristate
TEST	Wait on test control	Input
READY	Wait state control	Input
RESET	System reset	Input
NMI	Non-maskable interrupt request	Input
INTR	Interrupt request	Input
CLK	System clock	Input
V_CC	+5V	Power supply input
GND	Ground	Power Supply ground

The status signals on S₃ and S₄ specify the segment register used for calculating Physical address. The output on the status lines S₃ and S₄ when the processor is accessing various segments listed in next table.

Status Signal During Memory Segment Access

The status lines S₃ and S₄ can be used to expand the memory up to 4 Mb. The status line S₅ indicates the status of the 8086 interrupt enable flag. A low on the line S₆ indicates that the 8086 is on the bus (i.e., it indicates that 8086 is the bus master) and during hold acknowledge, this pin is driven to high impedance state. The output signal BHE on the first T-state of a bus cycle is maintained as status signal SI during all other T-states of the bus cycles.

Status Signal		Segment Register
S₄	S₃	Segment Register
0	0	Extra Segment
0	1	Stack Segment
1	0	Code or no segment
1	1	Data Segment

The 8086 outputs a low on the BHE pin during read, write and interrupt acknowledge cycles when the data is to be transferred to the high order data bus. The BHE can be used in conjunction with address bit A₀(AD₀) to select memory banks.

When the processor reads from the memory or an IO location it asserts RD as low. The TEST input is tested by the WAIT instruction. The 8086 will enter a wait state after execution of the WAIT instruction, and it will resume execution only when TEST is made low by an external hardware. This is used to synchronize an external activity to the processor's internal operation. TEST input is synchronized internally during each clock cycle on the leading edge of the clock signal.

INTR is the maskable interrupt and INTR must be held high until it is recognized to generate an interrupt signal. NMI is the non-maskable interrupt input activated by a leading edge signal.

RESET is the system reset input signal. For power-ON reset, it is held high for 50
microseconds. For reset while working, it is held high for at least four clock cycles. When the processor is reset, the DS, SS, ES, IP and flag register are cleared, Code Segment (CS) register is initialized to FFFF_H and queue is emptied. After reset, the processor will start fetching instructions from the 20-bit physical address FFFF0_H.

READY is an input signal to the processor, used by the memory or IO devices to get extra time for data transfer or to introduce wait states in the bus cycles. Normally READY is tied high. If the READY is tied low, the 8086 introduces wait states after second T-state of a bus cycle and it will complete the bus cycle only when READY is made high again.

CLK input is the clock signal that provides the basic timing for the 8086 and bus controller. The 8086 does not have an on-chip clock generation circuit. Hence the 8284 clock generator chip is used to generate the required clock. A quartz crystal whose frequency is thrice that of internal clock of an 8086 must be connected to the 8284. The 8284 generates the clock at crystal frequency. The 8284 divides the generated clock by three and modifies the duty cycle to 33% and output on CLK pin of 8284. This CLK output of 8284 must be connected to the 8086 CLK pin. The 8284 also provides the RESET and READY signals to the 8086. The maximum mode and minimum mode signals and maximum mode and minimum mode operations will discuss on upcoming posts.

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