8086 Maximum Mode Signals and Maximum Mode Based System

Maximum mode signals

The maximum mode signals of 8086 are listed in table below. The 8086 can made to work in maximum mode by grounding MN/MX. In maximum mode, the pin 24 to pin 31 are defined as follows.

Name	Description/Function	Type
RQ/GT1, RQ/GT0	Request/Grant bus access control	Bidirectional
LOCK	Bus priority block control	Output, Tristate
S2, S1, S0	Bus cycle status	Output, Tristate
QS1, QS0	Instruction queue status	Output

1. S₀, S₁, S₂: These are status signals and they used by the 8288 bus controller to generate the bus timing and control signals. The status signals are decoded as shown in table:



Status Signal			Machine Cycle
S2	S1	S0
0	0	0	Interrupt acknowlegement
0	0	1	Read IO port
0	1	0	Write IO port
0	1	1	Halt
1	0	0	Code access
1	0	1	Read memory
1	1	0	Write memory
1	1	1	Passive/Inactive



2. RQ/GT₀, RQ/GT₁(Bus Request/Bus Grant): These requests are used by the other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle. These pins are bidirectional. The request on GT₀ will have higher priority than GT₁.



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The bus request to 8086 work as follows:


1. When a local bus master requires system bus control, it sends a low pulse to the 8086.
2. At the end of the current bus cycle, the processor (8086) drives its pins to high impedance state and sends an acknowledge as a low pulse on the same pin to the device which requested the bus control.
3. On receiving the acknowledge the local master will take control of the system bus. After completing its work, at the end, the local bus master sends a low signal on the same pin to the 8086 to inform the end of control. Now 8086 regains the control of the bus.

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3. LOCK: It is an output signal, activated by the LOCK prefix instruction and remains active until the completion of the instruction prefixed by LOCK. The 8086 outputs low on the LOCK pin while executing an instruction prefixed by LOCK to prevent other bus masters from gaining control of the system bus.
4. QS₁,QS₀(Queue Status): The processor provides the status of queue on these lines. The queue status can be used by the external device to track the internal status of the queue in the 8086. The QS₀ and QS₁ are valid during the clock period following any queue operation. The output on QS₀ and QS₁ can be interpreted as shown in table.

Status Signal		Segment Register
QS1	QS0
0	0	No operation
0	1	First byte of an opcode from queue
1	0	Empty the queue
1	1	Subsequent byte from queue

Maximum Mode 8086 Based System

In maximum mode 8086-based system, an external bus controller 8288 has to be employed to generate the bus control signals. The 8288 can be configured for uniprocessor or multiprocessor mode of operation using the signals, \(\overline{AEN}\), IOB and CEN. The formation of address bus and data bus in 8086-based maximum mode system is shown in figure. For maximum mode of operation, the pin \(MN/\overline{MX}\) of 8086 processor is tied to the ground.

The system shown in figure employs a bus controller 8288 to generate bus control signals. Here the bus controller is configured for the uniprocessor mode of operation by grounding \(\overline{AEN}\) and IOB, and by applying +5 -V to CEN. (For multiprocessor mode of operation, IOB should be tied to +5-V and the signals \(\overline{AEN}\) and CEN are supplied by a bus arbiter such as INTEL 8289.)

In 8086 processor, the address is multiplexed with the data or status signals. In a system, multiplexing is not allowed and so the multiplexed address lines of the CPU bus has to be demultiplexed by using external latches. In the system shown in figure, three numbers of 8-bit latch 74LS573 are employed to demultiplex the address lines. The signal ALE generated by the bus controller is used as enable for the latches. In 8086-based system. the data bus should be provided with data transceivers to drive the data on the bus. In the system shown in figure, two numbers of bidirectional buffer 74LS245 are employed as data transceivers. The signals DEN and \(DT/\overline{R}\) generated by the bus controller are used as enable and direction control of buffers respectively.

The system employs a clock generator INTEL 8284 to generate the clock, reset and ready signals for the 8086 processor. A quartz crystal of frequency 15 MHz is connected to the X1 and X2 pins of 8284 so that the clock frequency supplied to the 8086 processor will be 5 MHz. An RC circuit is connected to the reset input of the 8284 to provide power-ON reset. A switch is also connected across the capacitor to provide manual reset.

The bus controller generates separate read and write controls for memory and IO devices. It also generates extended write control signal for memory and IO devices requiring higher write time.

Formation of system bus in 8086-based maximum mode system