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8086 Minimum Mode Signals and Minimum Mode Based System

Minimum Mode Signals

The minimum mode signals of an 8086 are listed in table below. For minimum mode of operation the MN/MX pin is tied to Vcc (logic high). In minimum mode, the 8086 itself generates all bus control signals. The minimum mode signals are explained below:
Name Description/Function Type
HOLD Hold request Input
HLDA Hold acknowledgement Output

WR		 Write control Output, Tristate

M/IO		 Memory/IO control Output, Tristate

DT/R		 Data transmit/Recieve Output, Tristate

DEN		 Data enable Output, Tristate
ALE Address latch enable Output

INTA		 Interrupt acknowledge Output
  1. DT/R(Data Transmit/Receive): It is an output signal from the processor to control the direction of data flow through the data transceivers.
  2. DEN(Data Enable) : It is an output signal from the processor used as output enable for the data transceivers.
  3. ALE(Address Latch Enable): It is used to demultiplex the address and data lines using external latches.
  4. M/IO: It is used to differentiate memory access and IO access. For IN and OUT instructions it is low. For memory reference instructions, it is high.
  5. WR: It is a write control signal and it is asserted low whenever the processor writes data to memory or IO port.
  6. INTA(Interrupt Acknowledge): The 8086 outputs low on this line to acknowledge when the interrupt request is accepted by the processor.
  7. HOLD: It is an input signal to the processor from other bus masters as a request to grant the control of the bus. It is usually used by DMA controller to get the control of bus.
  8. HLDA(Hold Acknowledge): It is an acknowledge signal by the processor to the master requesting the control of the bus through HOLD, The acknowledge is asserted high when the processor accepts the HOLD. [On accepting the hold, the processor drives all the tristate pins to high impedance state and sends an acknowledge to the device which requested HOLD. On receiving the acknowledge, the other master will take control of the bus.]

8086 Minimum Mode Based System

In minimum mode, the 8086 processor itself generates all bus control signals and so there is no need for an external bus controller. The 8086 processor has multiplexed address/data pins and address/status pins. In a system, multiplexing is not allowed and so the multiplexed address lines has to be demultiplexed by using external latches and the latches are enabled by using the signal ALE supplied by the processor. In an 8086-based system, the data bus should be provided with data transceivers to drive the data on the bus. The signal DEN is used as enable and the signal \(DT/\overline{R}\) is used as direction control for data transceivers.

The formation of address bus and data bus in the 8086-based minimum mode system is shown in figure. For minimum mode of operation the \(MN/ \overline{MX}\) is tied to Vcc(+5-V). The clock generator of the 8284 is used to generate the clock, reset and ready signals for the processor. A quartz crystal of frequency 15 MHz is connected to the X1 and X2 pins of 8284 so that the clock frequency supplied to the 8086 processor will be 5 MHz. An RC circuit is connected to the reset input of 8284 to provide power-ON reset. A switch is also connected across the capacitor to provide manual reset.

In the system shown figure below, three numbers of 8-bit latch 74LS573 are used as address latches and two numbers of 8-bit bidirectional buffer 74LS245 are used as data transceivers. The interfacing of memory and IO (or peripheral) devices.
Formation of system bus in 8086 based minimum mode system

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