VHDL Behavioral Description of all Logic Gates

AND Gate


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_gate is
port(
   a,b : in std_logic;
   s : out std_logic
);
end and_gate;
architecture Behavioral of and_gate is
begin
s<=a and b;
end Behavioral;

OR Gate


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate is
port(
   a,b : in std_logic;
   s : out std_logic
);
end or_gate;
architecture Behavioral of or_gate is
begin
s<=a or b;
end Behavioral;

NOT Gate


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity not_gate is
port(
   a : in std_logic;
   s : out std_logic
);
end not_gate;
architecture Behavioral of not_gate is
begin
s<=not(a);
end Behavioral;

NAND Gate


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand_gate is
port(
   a,b : in std_logic;
   s : out std_logic
);
end nand_gate;
architecture Behavioral of nand_gate is
begin
s<=a nand b;
end Behavioral;

NOR Gate


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nor_gate is
port(
   a,b : in std_logic;
   s : out std_logic
);
end nor_gate;
architecture Behavioral of nor_gate is
begin
s<=a nor b;
end Behavioral;

XOR Gate


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor_gate is
port(
   a,b : in std_logic;
   s : out std_logic
);
end xor_gate;
architecture Behavioral of xor_gate is
begin
s<=a xor b;
end Behavioral;

XNOR Gate


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xnor_gate is
port(
   a,b : in std_logic;
   s : out std_logic
);
end xnor_gate;
architecture Behavioral of xnor_gate is
begin
s<=a xnor b;
end Behavioral;

Comments

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